#include "MCF52259_IIC_driver.h"
#include "MCF52259_UART_driver.h"

void iic_init0(void)
{
	uint8 temp;
		
	MCF_GPIO_PASPAR=MCF_GPIO_PASPAR_SCL0_SCL0
					|MCF_GPIO_PASPAR_SDA0_SDA0;
//set I2C address	
	MCF_I2C0_I2ADR=MCF_I2C_I2ADR_ADR(0x12);
// 80,000/640=125KHz	
	MCF_I2C0_I2FDR=MCF_I2C_I2FDR_IC(0x3F);
	
	MCF_I2C0_I2CR=0|MCF_I2C_I2CR_IEN;
				 //|MCF_I2C_I2CR_IIEN
				 //|MCF_I2C_I2CR_TXAK
				 //|MCF_I2C_I2CR_MSTA

//if busy set to be slave module and send a top
	if(MCF_I2C0_I2SR&MCF_I2C_I2SR_IBB)
	{
//clear control register	
		MCF_I2C0_I2CR=0;
//enable module and send a START condition
		MCF_I2C0_I2CR=MCF_I2C_I2CR_IEN
					 |MCF_I2C_I2CR_MSTA;
//dummy read					 
		temp=MCF_I2C0_I2DR;
//clear status register		
		MCF_I2C0_I2SR=0;
//clear control register		
		MCF_I2C0_I2CR=0;
//enable the module
		MCF_I2C0_I2CR=MCF_I2C_I2CR_IEN;
	}
	
}

void iic_start0(void)
{
	while(MCF_I2C0_I2SR&MCF_I2C_I2SR_IBB) ;
	
	MCF_I2C0_I2CR|=MCF_I2C_I2CR_MTX;
	MCF_I2C0_I2CR|=MCF_I2C_I2CR_MSTA;
	
}

uint8 iic_sendbyte0(uint8 c)
{
	MCF_I2C0_I2DR=c;
	while((MCF_I2C0_I2SR&MCF_I2C_I2SR_IIF)==0)
	{
		;
	}
	MCF_I2C0_I2SR&=~MCF_I2C_I2SR_IIF;

//	while(MCF_I2C0_I2SR&MCF_I2C_I2SR_RXAK) ;
		
	if(MCF_I2C0_I2SR&MCF_I2C_I2SR_RXAK)
		return 0;//failed
	else
		return 1;//success
}

uint8 iic_receivebyte0(uint8 ack)
{
	uint8 temp;

	MCF_I2C0_I2CR&=~MCF_I2C_I2CR_MTX;

	if(ack)	//send acknowledge single 
		MCF_I2C0_I2CR&=~MCF_I2C_I2CR_TXAK;
	else  //no acknowledge single 
		MCF_I2C0_I2CR|=MCF_I2C_I2CR_TXAK;
	temp=MCF_I2C0_I2DR;
//	uart0_putchar(temp);
	while((MCF_I2C0_I2SR&MCF_I2C_I2SR_IIF)==0)
	{
		;
	}
	MCF_I2C0_I2SR&=~MCF_I2C_I2SR_IIF;
	temp=MCF_I2C0_I2DR;
//	uart0_putchar(temp);
	while((MCF_I2C0_I2SR&MCF_I2C_I2SR_IIF)==0)
	{
		;
	}
	MCF_I2C0_I2SR&=~MCF_I2C_I2SR_IIF;
	
	return temp;

}
void iic_stop0()
{

	MCF_I2C0_I2CR&=~MCF_I2C_I2CR_MSTA;
}
void iic_restart0()
{
	MCF_I2C0_I2CR|=MCF_I2C_I2CR_RSTA;
}


void iic_init1(void)
{
	uint8 temp;
		
	MCF_GPIO_PUCPAR=MCF_GPIO_PUCPAR_URTS2_SDA1
					|MCF_GPIO_PUCPAR_UCTS2_SCL1;
//set I2C address	
	MCF_I2C1_I2ADR=MCF_I2C_I2ADR_ADR(0x12);
// 80,000/640=125KHz	
	MCF_I2C1_I2FDR=MCF_I2C_I2FDR_IC(0x3F);
	
	MCF_I2C1_I2CR=0|MCF_I2C_I2CR_IEN;
				 //|MCF_I2C_I2CR_IIEN
				 //|MCF_I2C_I2CR_TXAK
				 //|MCF_I2C_I2CR_MSTA

//if busy set to be slave module and send a top
	if(MCF_I2C1_I2SR&MCF_I2C_I2SR_IBB)
	{
//clear control register	
		MCF_I2C1_I2CR=0;
//enable module and send a START condition
		MCF_I2C1_I2CR=MCF_I2C_I2CR_IEN
					 |MCF_I2C_I2CR_MSTA;
//dummy read					 
		temp=MCF_I2C0_I2DR;
//clear status register		
		MCF_I2C1_I2SR=0;
//clear control register		
		MCF_I2C1_I2CR=0;
//enable the module
		MCF_I2C1_I2CR=MCF_I2C_I2CR_IEN;
	}
	
}

void iic_start1(void)
{
	while(MCF_I2C1_I2SR&MCF_I2C_I2SR_IBB) ;
	
	MCF_I2C1_I2CR|=MCF_I2C_I2CR_MTX;
	MCF_I2C1_I2CR|=MCF_I2C_I2CR_MSTA;
	
}

uint8 iic_sendbyte1(uint8 c)
{
	MCF_I2C1_I2DR=c;
	while((MCF_I2C1_I2SR&MCF_I2C_I2SR_IIF)==0)
	{
		;
	}
	MCF_I2C1_I2SR&=~MCF_I2C_I2SR_IIF;

//	while(MCF_I2C0_I2SR&MCF_I2C_I2SR_RXAK) ;
		
	if(MCF_I2C1_I2SR&MCF_I2C_I2SR_RXAK)
		return 0;//failed
	else
		return 1;//success
}

uint8 iic_receivebyte1(uint8 ack)
{
	uint8 temp;

	MCF_I2C1_I2CR&=~MCF_I2C_I2CR_MTX;

	if(ack)	//send acknowledge single 
		MCF_I2C1_I2CR&=~MCF_I2C_I2CR_TXAK;
	else  //no acknowledge single 
		MCF_I2C1_I2CR|=MCF_I2C_I2CR_TXAK;
	temp=MCF_I2C1_I2DR;
//	uart0_putchar(temp);
	while((MCF_I2C1_I2SR&MCF_I2C_I2SR_IIF)==0)
	{
		;
	}
	MCF_I2C1_I2SR&=~MCF_I2C_I2SR_IIF;
	temp=MCF_I2C0_I2DR;
//	uart0_putchar(temp);
	while((MCF_I2C1_I2SR&MCF_I2C_I2SR_IIF)==0)
	{
		;
	}
	MCF_I2C1_I2SR&=~MCF_I2C_I2SR_IIF;
	
	return temp;

}
void iic_stop1()
{

	MCF_I2C1_I2CR&=~MCF_I2C_I2CR_MSTA;
}
void iic_restart1()
{
	MCF_I2C1_I2CR|=MCF_I2C_I2CR_RSTA;
}

void i2ccsb()
{
//	iic_init();
	char tmpa,tmpb;
	iic_start1();
	iic_sendbyte1(0xe8);
	iic_sendbyte1(2);
	iic_sendbyte1(0x8a);
	iic_stop1();
	
	delayms(100);
	
	iic_start1();
	iic_sendbyte1(0xe8);
	iic_sendbyte1(2);
	iic_sendbyte1(0x8a);
	iic_stop1();
	
	delayms(5);
	
	iic_start1();
	iic_sendbyte1(0xe9);
	tmpa=iic_receivebyte1(0);
	tmpb=iic_receivebyte1(0);
	iic_stop1();
	
	if(tmpa==0&&tmpb==0)
	{
			iic_start1();
			iic_sendbyte1(0xe8);
			iic_sendbyte1(2);
			iic_sendbyte1(0x8a);
			iic_stop1();	
	}
	
}